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Re: LYCCA - w-DSSSD Time Gated [message #17172 is a reply to message #17171] Wed, 13 August 2014 14:27 Go to previous messageGo to previous message
miree is currently offline  miree
Messages: 71
Registered: June 2014
continuous participant
From: *ikp.physik.tu-darmstadt.de
Hi,

yes... the TargetDSSSD times where not always present in the 2014 campaign Confused . I don't remember if there were similar problems in 2012. It could be that this module didn't read the TargetDSSSD time signals.
Here are the WallDSSSD unpackers. The Wall DSSSD times are read by the CAENv767 multihit TDCs. They have 128 channels, which is enough for one side of all DSSSD modules in each crate. Again I'm not sure if p- or n-side times are read. As far as I remember, these were always present.

While analyzing commissioning data, I never used these time signals. Perhaps someone in the LYCCA collaboration has experience in how this information can be used.

crate LyccaWallCrate1
   procid    70
   module    adc01   LYCCA.v785
   module    adc02   LYCCA.v785
   module    adc05   LYCCA.v785
   module    adc06   LYCCA.v785
   module    adc07   LYCCA.v785
   module    adc08   LYCCA.v785
   module    adc11   LYCCA.v785
   module    adc12   LYCCA.v785
   module    mhtdc   LYCCA.v767
end

crate LyccaWallCrate2
    procid    80
    module    adc13   LYCCA.v785
    module    adc14   LYCCA.v785
    module    adc17   LYCCA.v785
    module    adc18   LYCCA.v785
    module    adc19   LYCCA.v785
    module    adc20   LYCCA.v785
    module    adc23   LYCCA.v785
    module    adc24   LYCCA.v785
    module    mhtdc   LYCCA.v767
end
 
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