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PCIe-AS - What are limitations on Network size ? [message #917] Tue, 14 September 2004 15:47 Go to previous message
Walter F.J. Müller is currently offline  Walter F.J. Müller
Messages: 229
Registered: December 2003
Location: GSI, CBM
first-grade participant

From: lxg0311.gsi.de
During E. Denes talk on the 2nd FutureDAQ workshop the question was raised what the size limit of AS networks is.

In several places I found statements to the effect that the design goal for PCIe-AS was to support 'small' networks with a size of 1000 or 10000 nodes.

The turn pool size is 31 bits (see previous post). Each switch only requires as many bits in the turn pool as is needed to enumerate his ports. This allows to express a path through 10 8-port switches, or through 7 16-port switches, or through 6 32-port switches, more than enough to handle 1000 to 10000 end nodes.

The PNet based on 3 cascaded 8-port switches shown in my talk needes only a 9 bit path address. The BNet can in principle be build from two layers of 24-port swiches, so needs only 10 bit path addresses. So I assume, that even a combined BNet/PNet would not challenge the 31 bit path address length limit of PCIe-AS.

{16.9.2000: fixed DocuMana link which had changed...}


W.F.J.Müller, GSI, CBM, Tel: 2766

[Updated on: Thu, 16 September 2004 20:50]

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