GSI Forum: FutureDAQ - Networking » PCIe-AS - What are limitations on Network size ?

Home » FutureDAQ » FutureDAQ - Networking » PCIe-AS - What are limitations on Network size ?

Show: Today's Messages :: Polls :: Message Navigator

Re: PCIe-AS - What are limitations on Network size ? [message #924 is a reply to message #917]

Wed, 15 September 2004 11:10

Walter F.J. Müller
Messages: 229
Registered: December 2003
Location: GSI, CBM

first-grade participant

From: lxg0311.gsi.de

Walter F.J. Müller wrote on Tue, 14 September 2004 15:47

The PNet based on 3 cascaded 8-port switches shown in my talk needes only a 9 bit path address.

This isn't correct. Since 4 8-port switches have to be traversed, see the attached figure, one needs 4*3 = 12 bits.

At this place another correction: In my talk I mistakenly wrote that the PEX 8532 is a AS switch. It is a PCIe switch, a true AS switch is announced.

index.php?t=getfile&id=259

Attachment: 4switch.png
(Size: 14.33KB, Downloaded 1420 times)

W.F.J.Müller, GSI, CBM, Tel: 2766

Report message to a moderator

[Message index]

		PCIe-AS - What are limitations on Network size ? By: Walter F.J. Müller on Tue, 14 September 2004 15:47
		Re: PCIe-AS - What are limitations on Network size ? By: Walter F.J. Müller on Wed, 15 September 2004 11:10

Previous Topic:	Custom vs. commodity networks
Next Topic:	PCIe-AS - Tutorial -- Is there a CRC for the address header ?

Goto Forum:

-=] Back to Top [=-

[ Syndicate this forum (XML) ] [

] [

]

Current Time: Tue May 13 21:50:29 CEST 2025

Total time taken to generate the page: 0.00762 seconds