here is a first collection of the algorithms I implemented in our FPGA based frontend modules for
a PET detector readout (some of them were also mentioned in http://www.gsi.de/documents/DOC-2004-Apr-17-1.pdf):
1. Pulse detection / Zero suppression
The analog detector signals are continuously sampled by ADCs and the sampled data are processed
in FPGAs. To distinguish a signal pulse from background noise two summation windows are used, which
are compared with a threshold level. The size of the windows is selected in a way that the
uncorrelated noise should cancel out.
If there is no signal pulse, the sum values of both windows are nearly equal. If a pulse enters the
first window, the sum starts to rise and a trigger is generated if the sum is bigger than the
second window sum plus a threshold.
The value of the second window can also be used for pedestal correction of the sampled data.
2. Time reconstruction
After the pulse detection some pedestal corrected sample points are processed by the time reconstruction
algorithm. Until now there are two algorithms implemented:
- SAD Fit
In this iterative algorithm the detected rising edge of the signal is compared with a previously
generated set of data points with different phase shifts to the sample clock. Therefore an error
value is calculated for each data set which indicates its difference to the actual sampled data.
The minimum error value identifies the phase shift of the sampled data. The pulse time is then
expressed by: pulse detection clock count + phase shift.
- Mean Weighted Sum of Derivation
This algorithm is also operating on the rising edge of the detected signal pulse. At the beginning,
the first derivation of the data stream is calculated, followed by a search for the maximum value.
This gives the position of the turning point of the rising signal edge. Supposed the signal is almost
symmetric, the maximum and the adjacent values carry information about the phase shift of the signal.
Therefore, a sum is calculated from these values which are weighted with a time index and a binning value.
After the summation it is divided by the sum of sample values which results in a mean time value for
the rising edge. This value is then corrected to get again the time information in the format: clock
count + phase shift.
The timing resolutions are for both algorithms around 5 ns (SNR 10) and can reach up to 1 ns and shorter
for good SNR values (> 50).
[Updated on: Wed, 08 September 2004 14:28]
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