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Time protocols used for SADC
https://forum.gsi.de/index.phpindex.php?t=rview&goto=404&th=165#msg_404
How to interface SADC to Time distribution is described by Lars and Igor how the SADC is conceptually connected to the time distribution.
I wonder whether there is somewhere a more detailed documentation which describes:
how the TTC is used with the SADC in self-triggered operation
what time representation is distributed in this case by the TTC
what the hit and time stamp format is in the SADC data stream
]]>Walter F.J. Müller2004-05-01T19:01:27-00:00Re: Time protocols used for SADC
https://forum.gsi.de/index.phpindex.php?t=rview&goto=408&th=165#msg_408
1. in the triggered mode the time of the signal is referenced to the trigger time and in self triggered mode it is referenced to a time ZERO. The time ZERO is defined by the TCS when it broadcasts the RESET signal. The trigger and the RESET signals are synchronous to the TCS clock.
Each frontend module including SADC counts the TCS clock. The counter is reseted by the TCS RESET signal. In this case the value of the counter corrected by the propagation time of the clock through the fibre is an absolute time or a time stamp.
2. the SADC detects the signal, calculates the amplitude and the time. The time is given by the clock counter(time stamp) after which the signal appeared and by 5 bits which define the timing of the signal respectively to the clock phase within the clock period.
]]>Igor Konorov2004-05-02T17:21:02-00:00Re: Time protocols used for SADC
https://forum.gsi.de/index.phpindex.php?t=rview&goto=412&th=165#msg_412
Igor Konorov wrote on Sun, 02 May 2004 19:21
There is a diploma thesis of Alexander Mann ....
Thanks. Is this diploma thesis somewhere on the web ?
And to understand it more quantitatively:
How often is the RESET signal send by the TCS
How many bits does the clock counter have, and are all these bits transmitted in each time stamp for each hit.
1. the TCS controller sends RESET every 14 seconds. This time interval came from SPS duty cycle.
2. there are different implementations of the counter. In current version it has 30 bits.